1. Field of the Invention
The present invention relates to a semiconductor storage unit and in particular to a semiconductor storage unit with a plurality of banks.
2. Description of the Prior Art
FIG. 33 shows one example of electric configuration of the conventional semiconductor storage unit disclosed in Japanese Patent Application No. 9-305505, where (a) and (b) are a block diagram showing the electric configuration of the main part and a circuit diagram showing a configurational example of a circuit provided inside the block diagram shown in FIG. 33(a), respectively.
As shown in FIG. 33(a), the semiconductor storage unit of this example comprises two banks 2a and 2b with a plurality of subarrays 1, 1, . . . arranged in a matrix form. The banks 2a and 2b each comprise: the respective sense amplifier columns (SA) 3, 3, . . . and the respective subword driver columns (SWD) 4, 4, . . . for individual subarrays 1, 1, . . . the respective subword lines (SWL) 5, 5, . . . wired in the X direction (horizontal direction in the figure) of a subarray 1 for individual subarrays 1, 1, . . . ; and the respective bit lines (BL) 6, 6, . . . wired in the Y direction (vertical direction in the figure) of a subarray 1 for individual subarrays 1, 1, . . . ; the respective local I/O lines (LIO) 7, 7, . . . and the respective main word lies (MWL) 8, 8, . . . wired in the X direction of a subarray 1; and the respective column selection line (CSL) 9, 9, . . . wired in the Y direction of a subarray 1 for individual subarrays 1, 1, . . . .
Besides, provided in common to the banks 2a and 2b are global I/O lines (GIO) 11 connected to I/O amplifiers 10.sub.0 and 10.sub.1, comprising write amplifiers, data amplifier or the like in the Y direction of subarray 1, controlled by a logical sum of signals conveyed over a column selection line 9, and switch lines (SWIO) 12 which is wired in the same direction as the global I/O lines 11 with one for each arranging column of the global I/O lines 11 and along which signals RWSRj indicating the active state of columns for connecting local I/O lines 7 and global I/O lines 11 are conveyed.
Next, the operation of the semiconductor storage unit configured above will be described. First, when the bank 2a is selected in accordance with a signal RACTj conveyed over the signal line 13 for indicating the active state of the row, a main word line 8 and a sub-word line 5 provided on the bank 2a are activated and moreover a signal SE for activating the sense amplifier column 3 stands up. When a sub-word line 5 is activated, bit lines 6 connected to the sub-word line 5 are gradually activated. Besides, activation of the sense amplifier column 3 by the signal SE causes the leading of a signal SAP.
Next, at the same time when a column selection line 9 provided on any subarray 1 is activated, a switch line 12 for connecting a local I/O line 7 and a global I/O line 11 provided on the subarray 1 is activated. Thereby, the local I/O line 7 and the global I/O line 11 provided on the subarray 1 are connected, both of them are gradually activated, and the data written in the memory cell 14 present on a bit line 6 of a desired subarray 1 in the bank 2a are read out.
Thereafter, when the column selection line 9 and the switch line 12 in the bank 2a becomes inactive and a column selection line 9 and a switch line 12 in the bank 2b are activated instead, a local I/O line 7 and a global I/O line 11 provided on the subarray 1 in the bank 2b are connected, both of them are gradually activated, and the data written in the memory cell 14 present on a bit line 6 of a desired subarray 1 in the bank 2b are read out.
Incidentally, the operation till the column selection line 9 and the switch line 12 in the bank 2b are activated will be omitted, because of being almost similar to that in the bank 2a.